BQ24070 Datasheet, PDF (21/26 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

bq24070
www.ti.com
SLUS694A – MARCH 2006 – REVISED MARCH 2006
APPLICATION INFORMATION
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input. A 0.1-µF ceramic
capacitor, placed in close proximity to IN to VSS pins, works well. In some applications depending on the power
supply characteristics and cable length, it may be necessary to add an additional 10-µF ceramic capacitor to the
input.
The bq24070 only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed between
the OUT and VSS pin is typically sufficient.
It is recommended to install a minimum of 33-µF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
Thermal Considerations
The bq24070 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad to
provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θ_JA is:
q_JA
+
T_J
*
P
T_A
(9)
where
T_J = chip junction temperature
T_A = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θ_JA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 10:
P + ^ƪǒV_IN * V_OUT^{Ǔ ǒ}I_OUT ) I_BAT^Ǔƫ ) ^ƪǒV_OUT * V_BAT^{Ǔ ǒ}I_BAT^Ǔƫ
(10)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum
battery voltage because the system board and charging device does not have time to reach a maximum
temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is
easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and
chargers power pad temperature.
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