TMS320DM6437 Datasheet, PDF (57/309 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6437
Digital Media Processor
SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007
Table 2-20. VPBE Terminal Functions
SIGNAL
NAME
ZWT
NO.
HSYNC/EM_CS5/
GP[33]
F19
VSYNC/EM_CS4/
GP[32]
E19
VCLK/GP[31]
D19
VPBECLK/GP[30] G19
COUT0/EM_D[0]/
GP[14]
D16
COUT1/EM_D[1]/
GP[15]
D18
COUT2/EM_D[2]/
GP[16]
D17
COUT3/EM_D[3]/
GP[17]
E16
COUT4/EM_D[4]/
GP[18]
E18
COUT5/EM_D[5]/
GP[19]
E17
COUT6/EM_D[6]/
GP[20]
F16
COUT7/EM_D[7]/
GP[21]
F17
YOUT0/GP[22]/
(BOOTMODE0)
F18
YOUT1/GP[23]/
(BOOTMODE1)
F15
YOUT2/GP[24]/
(BOOTMODE2)
G15
YOUT3/GP[25]/
(BOOTMODE3)
G16
YOUT4/GP[26]/
(FASTBOOT)
G17
YOUT5/GP[27]
H17
YOUT6/
GP[28]
H16
YOUT7/
GP[29]
H15
LCD_OE/EM_CS3/
GP[13]
C18
G0/EM_CS2/
GP[12]
C19
B0/LCD_FIELD/
EM_A[3]/GP[11]
B18
ZDU ^TYPE(1)
NO.
J22 I/O/Z
H22 I/O/Z
G22 I/O/Z
K22 I/O/Z
E21 I/O/Z
G20 I/O/Z
E22 I/O/Z
F20 I/O/Z
G21 I/O/Z
F22 I/O/Z
F21 I/O/Z
H20 I/O/Z
J20 I/O/Z
K20 I/O/Z
L20 I/O/Z
H21 I/O/Z
K19 I/O/Z
L19 I/O/Z
J21 I/O/Z
K21 I/O/Z
D22 I/O/Z
C22 I/O/Z
D21 I/O/Z
OTHER ^{(2) (3)}
DESCRIPTION
VIDEO OUT (VPBE)
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the VPBE Horizontal Sync (I/O/Z).
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the VPBE Vertical Sync (I/O/Z).
This pin is multiplexed between VPBE and GPIO.
In VPBE mode, this pin is the VPBE Clock Output.
This pin is multiplexed between VPBE and GPIO.
In VPBE mode, this pin is the VPBE Clock Input.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT0.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT1.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT2.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT3.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT4.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT5.
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT6.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT7.
These pins are multiplexed between VPBE (VENC) and GPIO.
After reset, these are video encoder (VENC) outputs 6:0, YOUT[6:0].
For proper DM6437 device operation, the YOUT6 pin must be pulled
down via an external resistor.
For proper DM6437 device operation, the YOUT5 pin must be pulled
up via an external resistor.
This pin is multiplexed between VPBE (VENC) and GPIO.
In VPBE mode, this pin is the VENC output 7, YOUT7.
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, it is the LCD output enable LCD_OE (O/Z).
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Green output data bit 0,
G0.
IPD
DV_DD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Blue output data bit 0, B0
or LCD interlaced LCD_FIELD (I/O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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