TMS320DM6437 Datasheet, PDF (224/309 Pages) Texas Instruments – Digital Media Processor

TMS320DM6437
Digital Media Processor
SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007
www.ti.com
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode⁽¹⁾ (see Figure 6-22)
NO.
PARAMETER
-400
-500
-600
UNIT
MIN
MAX
18
t_d(PCLK-HDV)
Delay time, PCLK edge to HD valid
20
t_d(PCLK-VDV)
Delay time, PCLK edge to VD valid
22 t_{d(PCLK-C_FIELDV)} Delay time, PCLK edge to C_FIELD valid
2
9.5 ns
2
9.5 ns
2
9.5 ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
17
18
HD
VD
C_WE/C_FIELD
19
20
21
22
Figure 6-22. VPFE (CCD) Master Mode Control Output Data Timing
224 Peripheral Information and Electrical Specifications
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