TMS320DM6437 Datasheet, PDF (115/309 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6437
Digital Media Processor
SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007
Table 3-21. Multiplexed Pins on DM6437 (continued)
SIGNAL
NAME
YI5(CCD5)/GP[41]
YI4(CCD4)/GP[40]
YI3(CCD3)/GP[39]
YI2(CCD2)/GP[38]
YI1(CCD1)/GP[37]
YI0(CCD0)/GP[36]
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
HSYNC/EM_CS5/GP[33]
VSYNC/EM_CS4/GP[32]
VCLK/GP[31]
VPBECLK/GP[30]
YOUT7/GP[29]
YOUT6/GP[28]
YOUT5/GP[27]
YOUT4/GP[26]/(FASTBOOT)
YOUT3/GP[25]/(BOOTMODE3)
YOUT2/GP[24]/(BOOTMODE2)
YOUT1/GP[23]/(BOOTMODE1)
YOUT0/GP[22]/(BOOTMODE0)
COUT7/EM_D[7]/GP[21]
COUT6/EM_D[6]/GP[20]
COUT5/EM_D[5]/GP[19]
COUT4/EM_D[4]/GP[18]
COUT3/EM_D[3]/GP[17]
COUT2/EM_D[2]/GP[16]
COUT1/EM_D[1]/GP[15]
COUT0/EM_D[0]/GP[14]
LCD_OE/EM_CS3/GP[13]
G0/EM_CS2/GP[12]
B0/LCD_FIELD/EM_A[3]/GP[11]
R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)
G1/EM_A[1]/(ALE)/GP[9]/
(AEAW1/PLLMS1)
B1/EM_A[2]/(CLE)/GP[8]/
(AEAW0/PLLMS0)
R1/EM_A[0]/GP[7]/(AEM2)
R2/EM_BA[0]/GP[6]/(AEM1)
B2/EM_BA[1]/GP[5]/(AEM0)
EM_A[12]/PCBE3/GP[89]
EM_A[11]/AD24/GP[90]
EM_A[10]/AD23/GP[91]
EM_A[9]/PIDSEL/GP[92]
EM_A[8]/AD21/GP[93]
EM_A[7]/AD22/GP[94]
EM_A[6]/AD20/GP[95]
ZWT
NO.
C13
D14
B14
C14
B15
C15
D13
D12
F19
E19
D19
G19
H15
H16
H17
G17
G16
G15
F15
F18
F17
F16
E17
E18
E16
D17
D18
D16
C18
C19
B18
A17
A16
B16
B17
C17
C16
D10
C10
A9
D9
B9
C9
D8
ZDU
NO.
B16
C18
A16
B17
B18
B19
C17
C16
J22
H22
G22
K22
K21
J21
L19
K19
H21
L20
K20
J20
H20
F21
F22
G21
F20
E22
G20
E21
D22
C22
D21
B21
B20
A20
C21
E20
C20
B12
C12
B11
C11
A11
C10
B10
PINMUX DESCRIPTION
PINMUX GROUP
CONTROLLED BY PINMUX BIT FIELDS
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
CCDCSEL
CCDCSEL
CCDCSEL
CCDCSEL
CCDCSEL
CCDCSEL
AEM, CWENSEL
AEM, CFLDSEL
CS5SEL
CS4SEL
VENCSEL
VPBECKEN
VENCSEL
VENCSEL
VENCSEL
VENCSEL
VENCSEL
VENCSEL
VENCSEL
VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
AEM, VENCSEL
CS3SEL
AEM, RGBSEL
AEM, RGBSEL
AEM, RGBSEL
EMIFA/VPSS Sub-Block 1 AEM, RGBSEL
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
AEM, RGBSEL
AEM, RGBSEL
AEM, RGBSEL
AEM, RGBSEL
PCIEN, AEM
PCIEN, AEM
PCIEN, AEM
PCIEN, AEM
PCIEN, AEM
PCIEN, AEM
PCIEN, AEM
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Device Configurations 115