TMS320DM6437 Datasheet, PDF (109/309 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6437
Digital Media Processor
SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007
Table 3-19. PINMUX0 Register Bit Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
Sub-Block 0
EMIFA Pinout Modes
This field does not affect the actual EMIFA operation. It only determines what
multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]
CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]
Sub-Block 1
000b = No EMIFA Mode.
None of the multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.
COUT7/EM_D[7]/GP[21]
COUT6/EM_D[6]/GP[20]
001b = 8-bit EMIFA (Async) Pinout Mode 1.
(Up to 16M-Byte address reach per Chip Select Space).
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (Async or NAND) + 16-bit CCDC (VPFE) + 8-bit VENC (VPBE)
COUT5/EM_D[5]/GP[19]
COUT4/EM_D[4]/GP[18]
COUT3/EM_D[3]/GP[17]
COUT2/EM_D[2]/GP[16]
COUT1/EM_D[1]/GP[15]
010b = Reserved.
COUT0/EM_D[0]/GP[14]
2:0
AEM ⁽³⁾
011b = 8-bit EMIFA (Async) Pinout Mode 3.
G0/EM_CS2/GP[12]
B0/LCD_FIELD/EM_A[3]/GP[11]
(32K-Byte reach per Chip Select Space).
R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit G1/EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1)
EMIFA (Async or NAND) + 8-bit CCDC (VPFE) + 16-bit VENC (VPBE)
B1/EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0)
100b = 8-bit EMIFA (NAND) Pinout Mode 4.
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (NAND) + 8-bit CCDC (VPFE) + 16-bit VENC (VPBE)
R1/EM_A[0]/GP[7]/(AEM2)
R2/EM_BA[0]/GP[6]/(AEM1)
B2/EM_BA[1]/GP[5]/(AEM0)
101b = 8-bit EMIFA (NAND) Pinout Mode 5.
Sub-Block3
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit EM_A[12]/PCBE3/GP[89]
EMIFA (NAND) + 16-bit CCDC (VPFE) + 8-bit VENC (VPBE)
EM_A[11]/AD24/GP[90]
110b through 111b = Reserved
EM_A[10]/AD23/GP[91]
EM_A[9]/PIDSEL/GP[92]
EM_A[8]/AD21/GP[93]
EM_A[7]/AD22/GP[94]
EM_A[6]/AD20/GP[95]
EM_A[5]/AD19/GP[96]
The pin mux for these pins are controlled by a
combination of AEM and other PINMUX0 fields,
including CWENSEL, CFLDSEL, AEAW,
PCIEN, CI76SEL, CI54SEL, CI32SEL,
CI10SEL, VENCSEL, and RGBSEL. ⁽¹⁾
(3) The AEM default value is latched at reset from AEM[2:0] configuration inputs. The latched values are also shown at BOOTCFG.DAEM
(read-only).
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Device Configurations 109