THS8083T Datasheet, PDF (51/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

5.4.9.2 Closed Loop
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f(HS)
t(acq)
HS locking range
Lock-in time
t(JCS) Short-term jitter
t(JCL) Long-term jitter
See Note 16
See Note 16
TA = 25°C
TA = 25°C
15
100 kHz
5
12 ms
700 (p-p)
185 (rms)
ps
1250 (p-p)
440 (rms)
ps
700 (pk-pk)
185 (rms)
ps
1250 (p-p)
440 (rms)
ps
NOTE 16: PLL characterization:
• Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of
the clock rising edge. This is measured visually by capturing the clock and displaying it on a digital scope with a persistency of one
video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number of clock cycles (N = 800) are
captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between each
actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value along
one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
• Long term jitter in closed loop is defined as the variation over one video frame of the Nth clock rising edge on each line. This is
measured by capturing the time instant that a defined level on the rising edge of the Nth clock after HS is reached on each line. The
same principle for calculation is used as for short term jitter but now for one sample taken on every line and N = 800 lines.
5.4.10 Typical Plots (25°C and Measured for Standard VESA Graphics Formats)
NOTE: The THS8083 is configured for each video mode with I²C register settings as specified
in application note Using THS8083 for PC Graphics and Component Video Digitizing.
1500
POWER
vs
FREQUENCY
CURRENT
vs
FREQUENCY
350
1400
1300
1200
1100
1000
900
800
700
600
30 MHz Full-Scale
Sine Input
60 kHz Full-Scale
Ramp Input
300
Total Analog
250
AVDD_CH1+AVDD_CH2_3
200
Total Digital
AVDD_REF
150
DVDD
DVDD_PLL
100
AVDD_PLL
50
500
0
0
20
40
60
80
100
0
f – Frequency – MHz
50
100
f – Frequency – MHz
Figure 5–2. Power Consumption
5–7