THS8083T Datasheet, PDF (30/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

3.2.5 Register Name: NOM_INC_2
Subaddress: 04 (R/W)
MSB
NOM_INC23
NOM_INC22 NOM_INC21 NOM_INC20
NOM_INC[23..16]:
See register NOM_INC_0.
Default: 0xB9
NOM_INC19 NOM_INC18
NOM_INC17
LSB
NOM_INC16
3.2.6 Register Name: NOM_INC_3
Subaddress: 05 (R/W)
MSB
NOM_INC31
NOM_INC30 NOM_INC29 NOM_INC28
NOM_INC[31..24]:
See register NOM_INC_0.
Default: 0x70
NOM_INC27 NOM_INC26
NOM_INC25
LSB
NOM_INC24
3.2.7 Register Name: NOM_INC_4
Subaddress: 06 (R/W)
MSB
X
X
X
X
X
X
LSB
X
NOM_INC32
NOM_INC32:
See register NOM_INC_0
Default: 0x01
NOTE: The default value for NOM_INC is 0x 0170B9F645. Split into the 6-bit integer/ 27 bit fractional part, this can
be written as 0x2e.0b9f645 or 46.090802 in decimal format. From Appendix A, it can be calculated that this will
correspond to a DTO output frequency of 78.75 MHz (XGA@75Hz).
IMPORTANT: To properly update the increment it is required to program successively NOM_INC_0 to NOM_INC_4
and then repeat the programming of the two last bytes NOM_INC3 and NOM_INC4 in this order. By doing so, the
DTO will be properly set to the new frequency.
3.2.8 Register Name: VCODIV
Subaddress: 07 (R/W)
MSB
X
LSB
X
X
X
X
VCODIV2
VCODIV1
VCODIV0
VCODIV[2..0]:
Divider in analog PLL loop. Determines the internal master clock frequency as VCODIV x master clock
frequency (from XTL1–MCLK/XTL2).
Default: 0x03 i.e., analog multiplier of 8 producing an internal nominal frequency of 8x14.31818 MHz
VCO_DIV[2..0]
000
001
010
011 (default)
100
101
110
111
ANALOG PLL MULTIPLIER
5
6
7
8
9
10
11
12
3–6