THS8083T Datasheet, PDF (16/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

The clamp code is 8 bits wide and spans 128 ADC output codes (a 2 LSB change to clamp code corresponds
nominally to 1 LSB change in ADC output). The programmed clamp code is independent of the PGA setting (see
later). This ensures independent brightness/clamping control.
The clamp pulse defines the timing window during which the clamp circuit is internally enabled, and is either generated
externally and supplied to the device, or it can be internally generated. In the latter case, the user can program both
the position and width of the clamp pulse with respect to the horizontal sync (HS) input.
CLIP 255
255
ADC OUTPUT
CODE RANGE
0
CLIP 0
CLAMP CODE _{= +63 = 0 = –64}
+63
0
–64
191
63
VIN
CLIP 255
255
ADC OUTPUT
CODE RANGE
0
CLIP 0
CLAMP CODE
= +63 = 0 = –64
+63
0
–64
191
63
VIN
CLP PULSE
Influence of changing clamp codes on
A/D output, while keeping PGA gain setting
constant, in bottom-level clamp mode
Figure 2–2. Bottom-Level Clamping
CLP PULSE
Influence of changing clamp codes on
A/D output, while keeping PGA gain setting
constant, in midlevel clamp mode
Figure 2–3. Mid-Level Clamping
2.3 Composite Sync Slicer
The THS8083 includes a circuit that will compare the input signal on Ch.1 to a level 150 mV below the blanking level.
This slicer will output on the composite sync (CS) pin a 3-V compatible digital output. The intended use of this circuit
is for input video signals that have an embedded (negative or trilevel) sync. This is the case for workstation-type input
signals or the DTV analog interface that mandates sync-on-Y. Since the sync amplitude is ~300 mV, the slicing level
is at about 50% of the sync level. When enabled, the CS output is available even when the device is powered down.
CS will output the extracted composite sync. Since the PLL will be prevented from updating its phase detector while
the PFD_FREEZE pin is kept high, the user asserts PFD_FREEZE during the VBI (when CS has multiple transitions
per line). This puts the PLL in free-run. While it cannot be guaranteed with devices that have analog PLL’s, the digital
PLL in the THS8083 is assured to keep a constant output frequency and avoid frequency drift while the PLL is in
free-run. There is also no maximum on the time that PFD_FREEZE can be kept asserted to still keep a stable PLL
output frequency. In this case, the CS output can be directly connected to the THS8083’s HS input for purposes of
locking the PLL. However, the frequency monitoring of HS, that works off signal edges, will produce invalid numbers
on those lines where CS is present because of the multiple low-high transitions on these lines.
Alternatively, if an external sync separator is present that generates HS and VS from CS, the separated signals can
be fed to the corresponding inputs on the THS8083 and PFD_FREEZE can be left unused. As long as both signals
generate only 1 pulse per line respectively frame, the PLL will lock correctly and HS/VS frequency monitoring will be
accurate. Both options are shown in Figure 2–4.
2–2