THS8083T Datasheet, PDF(15/61 Page) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

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THS8083T Datasheet, PDF (15/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

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2 Functional Description

2.1 Analog Channel

The THS8083 contains three identical analog channels that are independently programmable. Each channel consists

of a clamping circuit, a programmable gain amplifier, and an A/D converter.

2.2 Clamping Circuit

The purpose of clamping is to provide the input signal with a known dc-value. Typically, video signals will be

ac-coupled into the part. The signal needs to be level-shifted to fall in the reference voltage range (VREFB...VREFT)

of the A/D converter. By supplying a programmable clamp, the user can shift the input signal with respect to the A/D

range. This has the same effect as keeping the input signal constant and applying offset to both A/D reference

voltages while keeping the VREFTâVREFB difference equal. However, no external adjustments are needed with this

implementation.

For video, the clamping circuit can only be active during the non-active video portion of each line to avoid changes

in brightness along the line. Clamping is done during the horizontal blanking interval, either on the backporch of sync

or during the sync tip (in the case of a sync present on at least one of the video channels). If HS is carried on a separate

line, as is typically the case for PC graphics, clamping is done during blanking. When the Y or G input channel contains

an embedded sync, then alternatively clamping can be done during the sync-tip. This is not supported on the

THS8083, since it is expected that the input signal level during clamping, of which position and width are determined

by the clamp timing pulse (as shown later) corresponds to the blanking level. Since (for RGB type inputs) the blanking

level will correspond to a low output code of the A/D, it makes sense to center the clamp range around an A/D output

code of 0. The user can adjust this level up or down, symmetrically around 0. If the clamping is set such that the

blanking level corresponds to a level below 0, the A/D output is clipped at code 0.

CLP

Reference Level

VIN

PGA 1

PGA 2

ADC

Bottom/Mid

Reference Level

Offset

DAC

Clamp DAC

Clamp Control

PGA Gain Control

Figure 2â1. Analog Channel Architecture

In the case of YUV input signals, blanking levels for U and V correspond to the mid-level analog input. To handle these

signals the clamping range should be centered on the mid-level output code of the A/D.

2â1

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