THS8083T Datasheet, PDF (50/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

5.4.8 Output Formatter/Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
fclk
fclk
tsu(OUT)
th(OUT),
th(DHS)
tsu(DHS)
tPLH(OE)
tPHL(OE)
Maximum conversion rate
Minimum conversion rate
Setup time
Hold time
Setup time
Propagation (delay) time, low-to-high
Propagation (delay) time, high-to-low-level output
DATACLK1 output duty cycle
With respect to 50% level of rising
edge on DATACLK
See Note 13
80
3
1
4
40%
MHz
10 MHz
ns
ns
ns
8.5
ns
8
58%
HS and data pipeline delay
See Note 14
See timing diagrams
NOTES: 13. Output timing – OE timing tPLH(OE) is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE timing tPHL(OE) is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output
levels. The digital output load is not higher than 10 pF.
14. Pipeline delay (latency) – The number of clock cycles between conversion initiation on an input sample and the corresponding output
data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
5.4.9 PLL
5.4.9.1 Open Loop
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DTO frequency range, f(DTO)
Instantaneous jitter, t(INS)
THS8083CPHP
Short-term jitter, t(JOS)
See Note 15
TA = 25°C
10
80
260 (p-p)
525 (p-p)
150 (rms)
900 (p-p)
360 (rms)
MHz
ps
ps
ps
Phase Increment
11.25
Monotonic
deg
NOTE 15: PLL characterization:
• Instantaneous jitter is the pk-pk variation of position of clock rising edge between succeeding periods.
• Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of
the clock rising edge. This can be measured visually by capturing the clock and displaying it on a digital scope with a persistency of
one video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number N of clock cycles (N = 800)
are captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between
each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value
along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
5–6