THS8083T Datasheet, PDF (31/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

3.2.9 Register Name: SELCLK
Subaddress: 08 (R/W)
MSB
X
X
X
X
LSB
X
X
SELCLK1
SELCLK0
SELCLK[1..0]:
Selects a clock divider on the DTO output., as shown below:
Default: 0x00 i.e., DTO divider = 1 (no additional division).
SEL_CLK[1..0]
00 (default)
01
10
11
DIVIDER CLKDIV
1
2
4
8
To cover the complete range 10 – 80 MHz, SELCLK needs to be changed as well, as shown in the PLL section.
3.2.10 Register Name: PHASESEL
MSB
X
X
X
PHASESEL4
PHASESEL[4..0]:
Sets the phase for the DTO clock output
Default: 0x10 i.e., phase shift = 180 degrees
PHASESEL3 PHASESEL2
Subaddress: 09 (R/W)
LSB
PHASESEL1 PHASESEL0
3.2.11 Register Name: PLLFILT
Subaddress: 0A (R/W)
MSB
X
LSB
X
GAIN_N2
GAIN_N1
GAIN_N0
GAIN_P2
GAIN_P1
GAIN_P0
GAIN_N[2..0]: PLL gain control: Sets the loop filter proportional time constant
Default: 0x7 (highest gain – lowest time constant)
GAIN_P[2..0]: PLL gain control: Sets the loop filter integrator time constant
Default: 0x7 (highest gain – lowest time constant)
NOTE:The higher the PLL gain setting, the less critical the initial DTO programming becomes since the device will
have a wider lock-in range. However, once lock is acquired, this means any jitter on HS will be amplified.
Therefore, for high jitter sources, it is recommended to apply more filtering once lock is acquired to filter out
this HS jitter.
3.2.12 Register Name: HS_WIDTH
Subaddress: 0B (R/W)
MSB
HS_WIDTH7
HS_WIDTH6
HS_WIDTH5
HS_WIDTH4
HS_WIDTH3 HS_WIDTH2 HS_WIDTH1
LSB
HS_WIDTH0
HS_WIDTH[7..0]:
Sets the width in pixels for HS detection. If the width of the incoming HS is less than this number, it is ignored.
The width in pixels of an incoming HS is incremented at each pixel following the active edge (of which the
polarity can be programmed, see HS_POL)
Default: 0x00
3–7