AM1806_15 Datasheet, PDF (51/245 Pages) Texas Instruments – AM1806 ARM® Microprocessor

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AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
Table 3-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL
NAME
NO.
GP7
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15] U2
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14] U1
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13] V3
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12] V2
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11] V1
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] W3
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
W2
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] /PRU1_R31[8]
W1
VP_DOUT[15/] LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]
P4
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
R3
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]
R2
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
R1
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]
T3
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]
T2
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]
T1
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]
U3
GP8
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]
/ PRU1_R31[27]
G1
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
G2
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
PRU1_R31[25]
J4
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
F1
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
F2
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
G4
AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0
F3
SPI0_SOMI /EPWMSYNCI / GP8[6] / MII_RXER
C16
SPI0_SIMO / EPWMSYNCO / GP8[5]
C18
SPI0_SCS[5] / UART0_RXD / GP8[4]
C19
SPI0_SCS[4] / UART0_TXD / GP8[3]
D18
SPI0_SCS[3] / UART0_CTS / GP8[2]
E17
SPI0_SCS[2] / UART0_RTS / GP8[1]
D16
GP8[0] ⁽¹⁾
K17
TYPE ⁽¹⁾
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PULL ⁽²⁾
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP30]
CP[30]
CP[30]
CP[30]
CP[31]
CP[31]
CP[31]
CP[31]
CP[6]
CP[7]
CP[7]
CP[8]
CP[8]
CP[9]
CP[9]
IPD
POWER
GROUP ⁽³⁾
DESCRIPTION
C
C
C
C
C
C
C
C
GPIO Bank 7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
GPIO Bank 8
C
A
A
A
A
A
A
A
B
(1) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
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