AM1806_15 Datasheet, PDF (144/245 Pages) Texas Instruments – AM1806 ARM® Microprocessor

AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
www.ti.com
6.16.2 SPI Electrical Data/Timing
6.16.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-35
through Figure 6-38).
Table 6-61. General Timing Requirements for SPI0 Master Modes⁽¹⁾
NO.
1 t_c(SPC)M
2 t_w(SPCH)M
3 t_w(SPCL)M
Cycle Time, SPI0_CLK, All Master Modes
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
4 t_{d(SIMO_SPC)M}
Delay, initial data bit valid on
SPI0_SIMO after initial edge
on SPI0_CLK⁽³⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5 t_{d(SPC_SIMO)M}
Delay, subsequent bits valid
on SPI0_SIMO after transmit
edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Output hold time, SPI0_SIMO _{from SPI0_CLK rising}
6 t_{oh(SPC_SIMO)M} valid after receive edge of
SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Polarity = 0, Phase = 1,
Input Setup Time, SPI0_SOMI _{to SPI0_CLK rising}
7 t_{su(SOMI_SPC)M} valid before receive edge of
SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Input Hold Time, SPI0_SOMI _{from SPI0_CLK rising}
8 t_{ih(SPC_SOMI)M} valid after receive edge of
SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
1.3V, 1.2V
MIN
MAX
20 ⁽²⁾
256P
0.5M-1
0.5M-1
5
1.1V
MIN
MAX
30 ⁽²⁾
256P
0.5M-1
0.5M-1
5
1.0V
MIN
MAX
40 ⁽²⁾
256P
0.5M-1
0.5M-1
6
UNIT
ns
ns
ns
-0.5M+5
5
-0.5M+5
5
-0.5M+6
ns
6
-0.5M+5
-0.5M+5
-0.5M+6
5
5
6
5
5
6
ns
5
5
6
5
5
6
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
ns
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.5
1.5
1.5
1.5
1.5
1.5
ns
1.5
1.5
1.5
1.5
1.5
1.5
4
4
5
4
4
5
ns
4
4
5
4
4
5
(1) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
144 Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1806