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AM1806_15 Datasheet, PDF (1/245 Pages) Texas Instruments – AM1806 ARM® Microprocessor | |||
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AM1806
SPRS658F â FEBRUARY 2010 â REVISED MARCH 2014
AM1806 ARM® Microprocessor
1 AM1806 ARM Microprocessor
1.1 Features
1
⢠375- and 456-MHz ARM926EJ-S⢠RISC MPU
⢠Enhanced Direct Memory Access Controller 3
(EDMA3):
â 2 Channel Controllers
â 3 Transfer Controllers
â 64 Independent DMA Channels
â 16 Quick DMA Channels
â Programmable Transfer Burst Size
⢠1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
DDR2 Interfaces)
⢠Two External Memory Interfaces:
â EMIFA
⢠NOR (8- or 16-Bit-Wide Data)
⢠NAND (8- or 16-Bit-Wide Data)
⢠16-Bit SDRAM with 128-MB Address Space
â DDR2/Mobile DDR Memory Controller with one
of the following:
⢠16-Bit DDR2 SDRAM with 256-MB Address
Space
⢠16-Bit mDDR SDRAM with 256-MB Address
Space
⢠Three Configurable 16550-Type UART Modules:
â With Modem Control Signals
â 16-Byte FIFO
â 16x or 13x Oversampling Option
⢠LCD Controller
⢠Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
⢠Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
Interfaces
⢠Two Master and Slave Inter-Integrated Circuits
( I2C Busâ¢)
⢠One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
⢠Programmable Real-Time Unit Subsystem
(PRUSS)
â Two Independent Programmable Real-Time Unit
(PRU) Cores
⢠32-Bit Load-Store RISC Architecture
⢠4KB of Instruction RAM per Core
⢠512 Bytes of Data RAM per Core
⢠PRUSS can be Disabled via Software to
Save Power
⢠Register 30 of Each PRU is Exported from
the Subsystem in Addition to the Normal R31
1
Output of the PRU Cores.
â Standard Power-Management Mechanism
⢠Clock Gating
⢠Entire Subsystem Under a Single PSC Clock
Gating Domain
â Dedicated Interrupt Controller
â Dedicated Switched Central Resource
⢠USB 2.0 OTG Port with Integrated PHY (USB0)
â USB 2.0 High- and Full-Speed Client
â USB 2.0 High-, Full-, and Low-Speed Host
â End Point 0 (Control)
â End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
⢠One Multichannel Audio Serial Port (McASP):
â Transmit and Receive Clocks
â Two Clock Zones and 16 Serial Data Pins
â Supports TDM, I2S, and Similar Formats
â DIT-Capable
â FIFO Buffers for Transmit and Receive
⢠Two Multichannel Buffered Serial Ports (McBSPs):
â Transmit and Receive Clocks
â Supports TDM, I2S, and Similar Formats
â AC97 Audio Codec Interface
â Telecom Interfaces (ST-Bus, H100)
â 128-Channel TDM
â FIFO Buffers for Transmit and Receive
⢠Video Port Interface (VPIF):
â Two 8-Bit SD (BT.656), Single 16-Bit or Single
Raw (8-, 10-, and 12-Bit) Video Capture
Channels
â Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
⢠Universal Parallel Port (uPP):
â High-Speed Parallel Interface to FPGAs and
Data Converters
â Data Width on Both Channels is 8- to 16-Bit
Inclusive
â Single-Data Rate or Dual-Data Rate Transfers
â Supports Multiple Interfaces with START,
ENABLE, and WAIT Controls
⢠Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
⢠Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
⢠One 64-Bit General-Purpose or Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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