AM1806_15 Datasheet, PDF (156/245 Pages) Texas Instruments – AM1806 ARM® Microprocessor

AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
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NO.
26
t_{d(SPC_SCSH)S}
27
t_{ena(SCSL_SOMI)S}
28
t_{dis(SCSH_SOMI)S}
Table 6-75. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽²⁾⁽³⁾ (continued)
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Required delay from final SPI1_CLK edge ^{from SPI1_CLK falling}
before SPI1_SCS is deasserted.
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
1.3V, 1.2V
MIN
MAX
0.5M+P+4
P+4
0.5M+P+4
P+4
P+15
P+15
1.1V
MIN
0.5M+P+5
MAX
P+5
0.5M+P+5
P+5
P+17
P+17
1.0V
MIN
0.5M+P+6
MAX
P+6
0.5M+P+6
P+6
P+19
P+19
UNIT
ns
ns
ns
156 Peripheral Information and Electrical Specifications
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