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LP3906SQ-JXXI Datasheet, PDF (5/47 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C ompatible
LP3906
www.ti.com
SNVS456M – AUGUST 2006 – REVISED MAY 2013
Pin Name
VIN2
SW2
GND_SW2
GND_C
GND_SW1
SW1
VIN1
SDA
SCL
EN_T
FB1
AVDD
VINLDO1
LDO1
ENLDO1
ENLDO2
GND_L
LDO2
VINLDO2
VinLDO12
FB2
ENSW1
SYNC
ENSW2
DAP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAP
I/O
I
O
G
G
G
O
I
I/O
I
I
I
I
I
O
I
I
G
O
I
I
I
I
I
I
GND
Pin Descriptions(1)
Type
Description
PWR Power in from either DC source or Battery to Buck 2
PWR Buck2 switcher output pin
G
Buck2 NMOS Power Ground
G
Non switching core ground pin
G
Buck1 NMOS Power Ground
PWR Buck1 switcher output pin
PWR
D
D
Power in from either DC source or Battery to buck 1
I2C Data (Bidirectional)
I2C Clock
D
Enable for preset power on sequence.
A
Buck1 input feedback terminal
PWR Analog Power for Buck converters.
PWR Power in from either DC source or Battery to input terminal of LDO1
PWR LDO1 Output
D
LDO1 enable pin, a logic HIGH enables the LDO1
D
LDO2 enable pin, a logic HIGH enables the LDO2
G
LDO Ground
PWR LDO2 Output
PWR Power in from either DC source or battery to input terminal to LDO2
PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)
A
Buck2 input feedback terminal
D
Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
D
Frequency Synchronization pin which allows the user to connect an external
clock signal PLL to synchronize the PMIC internal oscillator.
D
Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
GND
Connection isn't necessary for electrical performance, but it is recommended
for better thermal dissipation.
(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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