LP3906SQ-JXXI Datasheet, PDF (23/47 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C ompatible

LP3906
www.ti.com
SNVS456M – AUGUST 2006 – REVISED MAY 2013
NOTE
LP3906 The default Power on delays can be reprogrammed at final test or I²C to 1, 1.5, 2,
3, 6, or 11 ms.
LP3906 Default Power-Off Sequence
EN_T
Vout Buck1
t₁
Vout Buck2
Vout LDO1
t₂
t₃
Vout LDO2
t₄
Symbol
Description
Min
Typ
Max
Units
t₁
Programmable Delay from EN_T deassertion to V_CC_Buck1 Off
1.5
ms
t₂
Programmable Delay from EN_T deassertion to V_CC_Buck2 Off
2
ms
t₃
Programmable Delay from EN_T deassertion to V_CC_LDO1 Off
3
ms
t₄
Programmable Delay from EN_T deassertion to V_CC_LDO2 Off
6
ms
NOTE
LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or
10 ms. Default setting is the same as the on sequence.
Power-On-Reset
The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD <
V_POR. This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of
the Logic and the internal oscillator that clocks the Sequential Logic in the Control section.
I²C Compatible Serial Interface
I²C SIGNALS
The LP3906 features an I²C compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock
and data respectively. Both signals need a pull-up resistor according to the I²C specification. The LP3906
interface is an I²C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400 kbit/s. See
I²C specification from Philips for further details.
Copyright © 2006–2013, Texas Instruments Incorporated
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