LP3906SQ-JXXI Datasheet, PDF (24/47 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C ompatible

LP3906
SNVS456M – AUGUST 2006 – REVISED MAY 2013
www.ti.com
I²C DATA VALIDITY
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the
data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 34. I²C Signals: Data Validity
I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the
SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP
bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 35. START and STOP Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been
addressed must generate an acknowledgement (“ACK”) after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). Please note that according to industry I2C standards for 7-bit
addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most
significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte
selects the register to which the data will be written. The third byte contains data to write to the selected register.
LP3906 has a chip address of 60’h, which is factory programmed.
MSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1
LSB
R/W
bit0
1
1
0
0
0
0
0
I²C SLAVE address (chip address)
Figure 36. I²C Chip Address
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