LP3906SQ-JXXI Datasheet, PDF (25/47 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C ompatible

www.ti.com
ack from slave
LP3906
SNVS456M – AUGUST 2006 – REVISED MAY 2013
ack from slave
ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
SCL
SDA
1 2 3 4 5 6 7 8 9 1 2 3 ...
start
id = K¶60
w ack
addr = K¶02
ack
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3906 chip address : 0x60
Figure 37. I²C Write Cycle
DGGUHVV K¶$$ GDWD
ack stop
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
.
SDA
start
id = K¶60
w ack
register addr = K¶10 ack rs
id = K¶60
Figure 38. I²C Read Cycle
r ack
GDWD DGGU K¶6A
ack stop
LP3906 Control Registers
Register Address
0x02
0x07
0x10
0x11
0x20
0x23
0x24
0x25
0x29
0x2A
0x2B
0x38
0x39
0x3A
Register Name
ICRA
SCR1
BKLDOEN
BKLDOSR
VCCR
B1TV1
B1TV2
B1RC
B2TV1
B2TV2
B2RC
BFCR
LDO1VCR
LDO2VCR
Read/Write
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register Description
Interrupt Status Register A
System Control 1 Register
Buck and LDO Output Voltage Enable Register
Buck and LDO Output Voltage Status Register
Voltage Change Control Register 1
Buck 1 Target Voltage 1 Register
Buck 1 Target Voltage 2 Register
Buck 1 Ramp Control
Buck 2 Target Voltage 1 Register
Buck 2 Target Voltage 2 Register
Buck 2 Ramp Control
Buck Function Register
LDO1 Voltage control Registers
LDO2 Voltage control Registers
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3906
Submit Documentation Feedback
25