LP3906SQ-JXXI Datasheet, PDF (26/47 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C ompatible

LP3906
SNVS456M – AUGUST 2006 – REVISED MAY 2013
INTERRUPT STATUS REGISTER (ISRA) 0X02
This register informs the user of the temperature status of the chip.
Name
Access
Data
Reset
D7-2
—
—
Reserved
0
D1
Temp 125°C
R
Status bit for thermal warning PMIC T>125°C
0 – PMIC Temp. < 125°C
1 – PMIC Temp. > 125°C
0
www.ti.com
D0
—
—
Reserved
0
CONTROL 1 REGISTER (SCR1) 0X07
This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM
and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.
The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through
assertion of the EN_T pin.
Name
Access
Data
D7
—
—
Reserved
Reset 0
D6-4
EN_DLY
R/W
Selects the preset
delay sequence from
EN_T assertion
(shown below)
D3
—
—
Reserved
010
1
D2
FPWM2
R/W
Buck 2 PWM /PFM
Mode select
0 – Auto Switch PFM -
PWM operation
1 – PWM Mode Only
0
D1
FPWM1
R/W
Buck 1 PWM /PFM
Mode select
0 – Auto Switch PFM -
PWM operation
1 – PWM Mode Only
0
D0
ECEN
R/W
External Buck Clock
Select
0 – Internal 2 MHz
Oscillator clock
1 – External 13 MHz
Oscillator clock
0
EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
EN_DLY<2:0>
000
001
010
011
100
101
110
111
Buck1
1
1
1.5
1.5
1.5
1.5
3
2
Buck2
1
1.5
2
2
2
1.5
2
3
Delay (ms)
LDO1
1
2
3
1
3
2
1
6
LDO2
1
2
6
1
6
2
1.5
11
BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10
This register controls the enables for the Bucks and LDOs.
Name
Access
Data
Reset
D7
—
—
Reserved
0
D6
LDO2EN
R/W
0 – Disable
1 – Enable
1
D5
—
—
Reserved
1
D4
LDO1EN
R/W
0 – Disable
1 – Enable
1
D3
—
—
Reserved
0
D2
BK2EN
R/W
0 – Disable
1 – Enable
1
D1
—
—
Reserved
0
D0
BK1EN
R/W
0 – Disable
1 – Enable
1
26
Submit Documentation Feedback
Product Folder Links: LP3906
Copyright © 2006–2013, Texas Instruments Incorporated