GC3011A Datasheet, PDF (5/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
To read from a control register the processor must set A[0:3] to the desired address, set CE low,
and then set RE low. The chip will then drive C[0:7] with the contents of the selected register. After the
processor has read the value from C[0:7] it should set RE and CE high. The C[0:7] pins are turned off (high
impedance) whenever CE is high or WE is low. The chip will only drive these pins when both CE and RE
are low and WE is high.
If RE is held low, then the interface will behave in the GC3011 mode, where CE is CS, and WE is
R/W.
2.2 SYNC CIRCUIT
The sync circuit is used to synchronize the chip during diagnostics or system initialization. The sync
circuit includes a 20 bit counter which can be programmed to generate terminal count (TC) sync pulses
every 2⁸, 2¹², 2¹⁶ or 2²⁰ input clock cycles. The counter can be synchronized to the SI sync input, or left to
free run. The SI and TC sync pulses can be used to synchronize or clear the counters, accumulators or state
machines found within the rest of the chip. The lower 12 bits of the counter are used as input samples to
the resampler during diagnostics.
The user may select which sync signal is output from the chip on the SO pin. The SO signal can be
either a delayed version of the sync input, the counter’s TC sync, or a one-shot pulse. The sync output signal
is one clock cycle wide, synchronized to the output clock (OCK).
2.3 INTERPOLATION FILTER
The interpolation filter is used to interpolate between input data samples in order to generate output
samples at fractional time delays relative to the input samples. The filter is a 15 tap FIR filter with 4096 sets
of coefficients. Each set of coefficients corresponds to a different time delay between input samples. The
circuit accepts a new delay control word (12 bits) every clock cycle which tells it which set of coefficients to
use during that clock cycle. This allows the interpolation time delays to vary every clock sample.
Interpolating to 4096 delay values gives a worst case phase error (phase jitter) of +/- 360/8192 = +/- 0.09
degrees.
The delay control word can either come from the interpolation control circuit described below, or
from an external source. The external input allows multiple resamplers to be synchronized to controls
coming from a common resampler chip in a master/slave arrangement.
2.4 INTERPOLATION CONTROL
The interpolation control circuit is used to generate the time delay control words used by the
interpolation filter. The interpolated output rate is specified as the ratio of the input rate to the output rate.
This ratio is limited to be within the range of 1 to 4 and is formatted as a 32 bit word. The most significant 2
bits are the integer portion of the ratio and the lower thirty bits are the fractional part. This ratio is equivalent
to the ratio of the output sample spacing to the input sample spacing. The interpolation ratio feeds a 32 bit
accumulator. The 2 bit integer portion of the accumulator’s output is used to determine the number of input
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