GC3011A Datasheet, PDF (22/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
4.3 A AND B RATE-LOCK-LOOP (RLL) COEFFICIENT REGISTERS
Registers 6, and 7 contain the 5 bit A and B coefficients used in the RLL circuit.
ADDRESS 6:
A REGISTER
BIT
TYPE
0-4
R/W
5-7
R/W
NAME
A[0:4]
unused
DESCRIPTION
The A coefficient
ADDRESS 7:
B REGISTER
BIT
TYPE
NAME
DESCRIPTION
0-4
R/W
B[0:5]
The B coefficient
5
R/W
ERR_POL
Invert the polarity of the EIN signal. Normally a high
level on EIN will increase the resampling ratio
(which decreases the output rate). With ERR_POL
high a high level on EIN will decrease the
resampling ratio (which increases the output rate).
6,7
R/W
LOAD_AB
The sync mode for loading A and B into the RLL
circuit. See Table 1 in Section 4.4 for details.
The A and B coefficients range from 0 to 31. The FIFO error in the RLL is multiplied by 2^-A and 2^-B
when A and B are non-zero. If A or B are zero, then the error for that path (See Figure 2) is cleared.
After loading the A and B coefficients, the user can choose, using the LOAD_AB control bits, to
have them take effect immediately, or when a sync event occurs.
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice