GC3011A Datasheet, PDF (12/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
2.8.4 Selecting External Components for the PLL
The recommended analog supply filter and loop filter is shown in Figure 5.
VCC
AVCC
CVIN
GC3011A
CVOUT
AGND
GND
LOOP FILTER
SUPPLY FILTER
Analog Vcc
47 Ohms
Control Voltage
R
10uF ^0.1uF
C₂
C₁
Analog Gnd
47 Ohms
Digital V_CC
Digital GND
Figure 5. Supply and Loop Filters
All components shown in figure 5 should be placed as close as possible to the package. CVIN and
CVOUT should be shorted together. Separate CVIN and CVOUT pins are provided for specialized
applications that need an active loop filter.
The supply filter is used to isolate the analog power pins from the noise on the digital supply. This
filter will cause a slight drop in the analog VCC voltage. At 3.3 volts the drop is about 0.1 volts.
The PLL bandwidth and damping are set by the resistor R and the capacitors C₁ and C₂. The
resistor R sets the loop gain K
The PLL uses a third order loop to reduce jitter due to voltage across R while the pump current is
active. The third order loop is accomplished using a second capacitor C₂, which should be significantly
smaller than C₁. Generally, C₂ = C₁ / 100
Suggested values for R, C₁ and C₂ are R=220 Ohms, C1=0.22 uF, and C2 = 0.0022uF
2.8.5 External Output Clock Mode
The FIFO output can be clocked using an externally provided clock. Samples will be output from
the chip synchronous to the rising edge of this clock. This mode is used when the user has an external
output clock, or when multiple chips are being synchronized to an output clock generated by one of a bank
of resampler chips. In this mode the OCK clock pin is driven by the external clock.
2.9 POWER DOWN MODES
The chip has a power down and clock loss detect circuit. This circuit detects if the clock is absent
long enough to cause dynamic storage nodes to lose state. If clock loss is detected, an internal reset state
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