GC3011A Datasheet, PDF (29/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
4.9.3 READ PLL STATUS
If STATUS_SELECT is 2 the PLL status is read from addresses 14 and 15.
ADDRESS 14: Status Register 0, STATUS_SELECT=2
BIT
TYPE
0-3
R
4-7
R
NAME
LENGTH[0:3]
DIVIDE[0:3]
DESCRIPTION
The current VCO length setting.
The current VCO divide setting.
ADDRESS 15: Status Register 1, STATUS_SELECT=2
BIT
TYPE
0-3
R
4
R
5
R
6,7
R
NAME
DESCRIPTION
STATE[0:3]
BUSY
LOCK
LOCK_STATE[0:1]
The current PLL acquisition state. Zero is reset and
15 is acquired.
This bit is high when acquisition is in progress or
has not started. This bit is forced low if the
FORCE_LENGTH and FORCE_DIVIDE bits are
both high.
Indicates that the PLL is in a lock state.
Indicates the lock state. During acquisition the state
is zero. After acquisition 0 means the PLL is in lock.
One means that the FIFO is too empty and the VCO
control voltage needs to be decreased (slows the
VCO). A two means that the FIFO is too full and the
VCO control voltage needs to be increased.
4.9.4 READ CHECKSUM
If STATUS_SELECT is 3 the checksum is read from addresses 14 and the keepalive clock status
is read from 15. Address 15 is only used for test purposes.
ADDRESS 14: Status Register 0, STATUS_SELECT=3
BIT
TYPE
0-7
R
NAME
CHECKSUM[0:7]
DESCRIPTION
The checksum (See Section 2.10).
ADDRESS 15: Status Register 1, STATUS_SELECT=3
BIT
TYPE
0
R
1
R
2
R
3
R
4-7
R
NAME
NO_IN_CK
PD_IN
NO_OUT_CK
PD_OUT
unused
DESCRIPTION
Input clock loss detected.
Input power down mode.
Input clock loss detected
Output power down mode.
Texas Instruments Incorporated
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