GC3011A Datasheet, PDF (4/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
2.0 FUNCTIONAL DESCRIPTION
Fabricated in 0.5 micron CMOS technology, the GC3011A chip is a general purpose digital
resampler chip designed to accurately reduce the sample rate of the input data stream by a fractional
amount ranging from 1.0 down to 0.25. The chip includes an interpolation control block, a multi-chip
synchronization and offset circuit, a 15 tap interpolation filter, a 16 word output FIFO memory, an output
clock generator and an interpolation ratio rate-lock loop (RLL) circuit. In addition, an output multiplexor
circuit allows the user to by-pass the FIFO and output the resampled samples directly. A control interface
allows the user to set the resampling modes, resampling rate and output clocking modes.
The multi-chip sync and offset circuit allows multiple GC3011A chips to be synchronized in a
master/slave configuration. The offset portion of the circuit allows each chip’s interpolation delay to be offset
by a fixed amount relative to the other chips.
The GC3011A chip accepts input rates up to 100 MHz.
The chip can operate in a fixed resampling mode where the user specifies the desired output rate,
or the chip can be configured to adapt the resampled rate to match an externally provided output clock. The
resampled data can be output synchronous to the input clock or can be output synchronous to the output
clock. When output synchronous to the input clock the samples are accompanied by a data valid flag to
indicate which samples are valid and which are invalid. When output synchronous to the output clock the
chip uses the internal 16 word FIFO to smooth the data. The output clock can be provided externally, or can
be generated within the chip using the internal oscillator which is locked to the resampled data rate.
The chip does not provide any anti-alias filtering. The user must bandlimit the input signal before it
is down-sampled by the GC3011A chip. The GC2011A digital filter chip can be used for this purpose.
Fractional upsampling can be achieved by using the GC2011A digital filter chip to up sample the
signal by a factor of two before it is downsampled by the GC3011A.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus
consisting of an 8 bit data I/O port, a 4 bit address port, a read/write bit, and a control select strobe. The
chip’s 16 control registers (8 bits each) are memory mapped into the 4 bit address space of the control port.
2.1 CONTROL INTERFACE
The chip is configured by writing control information into sixteen control registers within the chip.
The contents of these control registers and how to use them are described in Section 4.0. The registers are
written to or read from using the C[0:7], A[0:3], RE, WE, and CE pins. Each control register has been
assigned a unique address within the chip. An external processor (a microprocessor, computer, or DSP
chip) can write into a register by setting A[0:3] to the desired register address, setting the CE pin low, setting
C[0:7] to the desired value and then pulsing WE low. RE must remain high
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