GC3011A Datasheet, PDF (25/38 Pages) Texas Instruments – 3.3V DIGITAL RESAMPLER CHIP

GC3011A 3.3V DIGITAL RESAMPLER
SLWS136A
4.6 OUTPUT MODE REGISTER
These register sets various output mode controls.
ADDRESS 10: Output Mode Register
BIT
TYPE
0-1
R/W
2
R/W
3
R/W
4
R/W
5
R/W
6,7
R/W
NAME
FIFO_RESET
BYPASS
Unused
DVAL_EARLY
DVAL_POL
Unused
DESCRIPTION
The FIFO is reset to half full according to Table 1 in
Section 4.4.
Turns off the FIFO so that the data and the data
valid flag bypass the FIFO and are output directly
from the chip. The OCK pin must be tied to the CK
pin in this mode.
Normally the DVAL is active for the clock cycle just
before the DO output changes. When this bit is set
the DVAL strobe comes out one clock earlier so that
it can be used as a clock enable to GRAYCHIP
devices which need the clock enable to be active
one clock earlier.
The DVAL strobe is normally active high. DVAL is
active low when DVAL_POL is high.
Texas Instruments Incorporated
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