DS125BR401SQ Datasheet, PDF (5/52 Pages) Texas Instruments – Low-Power 12.5-Gbps 4-Lane Repeater With Input Equalization and Output De-Emphasis

DS125BR401
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SNLS419C – JULY 2012 – REVISED APRIL 2013
Pin Descriptions⁽¹⁾ (continued)
Pin Name
Pin Number
I/O, Type
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
LPBK
23
I, 4-LEVEL,
LVCMOS
VDD_SEL
25
I, FLOAT
PWDN
52
I, LVCMOS
ALL_DONE
27
O, LVCMOS
Power
VIN
VDD
24
Power
9, 14,36, 41, 51 Power
GND
DAP
Power
Pin Description
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50Ω or >50KΩ termination to the power rail is enabled.
See Table 4.
Controls the loopback function
Tie 1kΩ to GND = Root Complex Loopback (INA_n to OUTB_n
Float = Normal Operation
Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
Controls the internal regulator
Float = 2.5V mode
Tie GND = 3.3V mode
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 4.
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
Power supply pins CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 µF cap to each VDD pin
Ground pad (DAP - die attach pad).
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