DS125BR401SQ Datasheet, PDF (35/52 Pages) Texas Instruments – Low-Power 12.5-Gbps 4-Lane Repeater With Input Equalization and Output De-Emphasis

DS125BR401
www.ti.com
SNLS419C – JULY 2012 – REVISED APRIL 2013
APPLICATIONS INFORMATION
The DS125BR401 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high
speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional
information on QFN (WQFN) packages.
EXTERNAL MICROSTRIP
100 mils
20 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
VDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ¹
19
54
20
53
21
52
22
51
23
BOTTOM OF PKG
50
GND
24
49
25
48
26
47
27
46
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 6. Typical Routing Options
The graphic shown above depicts different transmission line topologies which can be used in various
combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be
minimized or eliminated by increasing the swell around each hole and providing for a low inductance return
current path. When the via structure is associated with thick backplane PCB, further optimization such as back
drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.
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