DS125BR401SQ Datasheet, PDF (22/52 Pages) Texas Instruments – Low-Power 12.5-Gbps 4-Lane Repeater With Input Equalization and Output De-Emphasis

DS125BR401
SNLS419C – JULY 2012 – REVISED APRIL 2013
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WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Table 10 for more information.
Address
Register Name
0x00
Observation
0x01
PWDN Channels
Table 10. SMBUS Slave Mode Register Map
Bit
7
6:3
Field
Reserved
Address Bit
AD[3:0]
2
EEPROM Read
Done
1
Reserved
0
Reserved
7:0 PWDN CHx
Type
R/W
R
R
R/W
R/W
R/W
Default
0x00
0x00
Description
Set bit to 0.
Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
1: Device completed the read from external
EEPROM.
Set bit to 0.
Set bit to 0.
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Note: override PWDN pin.
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