DS125BR401SQ Datasheet, PDF (14/52 Pages) Texas Instruments – Low-Power 12.5-Gbps 4-Lane Repeater With Input Equalization and Output De-Emphasis

DS125BR401
SNLS419C – JULY 2012 – REVISED APRIL 2013
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PWDN
(PIN 52)
0
0
0
0
1
RXDET
(PIN 22)
0
Tie 20kΩ
to GND
Float
(Default)
1
X
Table 4. RX-Detect Settings
SMBus REG
bit[3:2]
Input Termination
00
Hi-Z
01
Pre Detect: Hi-Z
Post Detect: 50 Ω
10
Pre Detect: Hi-Z
Post Detect: 50 Ω
11
50 Ω
High Impedance
Recommeded
Use
X
PCIe only
PCIe only
All Others
X
Comments
Manual RX-Detect, input is high impedance mode
Auto RX-Detect, outputs test every 12 msec for 600
msec then stops; termination is Hi-Z until RX
detection; once detected input termination is 50 Ω
Reset function by pulsing PWDN high for 5 usec
then low again
Auto RX-Detect, outputs test every 12 msec until
detection occurs; termination is Hi-Z until RX
detection; once detected input termination is 50 Ω
Manual RX-Detect, input is 50 Ω
Power down mode, input is Hi-Z, output drivers are
disabled
Used to reset RX-Detect State Machine when held
high for 5 usec
RX-Detect in SAS/SATA (up to 6 Gbps) Applications
Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications
sequence to detect and communicate between Controllers/Expanders and target drives. This communication
eliminates the need to detect for endpoints like PCIe. For SAS/SATA systems, it is recommended to tie the
RXDET pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target
drive without any additional latency due to the termination detection sequence defined by PCIe.
Table 5. Signal Detect Threshold Level⁽¹⁾
SD_TH (PIN 26)
0
R
F (default)
1
SMBus REG bit [3:2] and [1:0]
10
01
00
11
Assert Level (typ)
210 mVp-p
160 mVp-p
180 mVp-p
190 mVp-p
(1) VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
De-assert Level (typ)
150 mVp-p
100 mVp-p
110 mVp-p
130 mVp-p
MODE
(PIN 21)
0
R
F (default)
1
Table 6. MODE operation with Pin Control
Driver Characteristics
Limiting
Transparent without DE
Automatic
Transparent with DE
PCIe
X
SAS
SATA
X
10G-KR
10GbE
X
X
CPRI
OBSAI
X
SRIO
(R)XAUI
X
Interlaken
Infiniband
X
Note: Automatic operation allows input to sense the incoming data-rate and utilize a "Transparent" output driver
for operation at or above 8 Gbps.
Note: SAS/SATA up to 6 Gbps.
MODE operation with SMBus Registers
When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In
order to override this control function, Register 0x08[2] must be written with a "1". Writting this bit enables MODE
control of each channel individually using the channel registers defined in Table 7.
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