DS125BR401SQ Datasheet, PDF (10/52 Pages) Texas Instruments – Low-Power 12.5-Gbps 4-Lane Repeater With Input Equalization and Output De-Emphasis

DS125BR401
SNLS419C – JULY 2012 – REVISED APRIL 2013
TIMING DIAGRAMS
(OUT+)
VOD (p-p) = (OUT+) ± (OUT-)
(OUT-)
80%
0V
20%
t_RISE
80%
20%
t_FALL
Figure 1. CML Output and Rise and FALL Transition Time
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+
IN
0V
-
t_PLHD
+
OUT
0V
-
t_PHLD
Figure 2. Propagation Delay Timing Diagram
+
IN
DATA
0V
-
t_IDLE-DATA
+
t_DATA-IDLE
OUT
DATA
0V
-
IDLE
IDLE
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
t_LOW
t_R
t_HIGH
t_BUF
t_HD:STA
t_HD:DAT
t_F
t_SU:DAT
t_SU:STA
t_SU:STO
SP
ST
ST
SP
Figure 4. SMBus Timing Parameters
SCL
SDA
10
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