DRV3204-Q1_15 Datasheet, PDF (5/38 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
ESD ⁽¹⁾
ESD all pins
ESD performance of all pins to any other
pin
HBM model
CDM model
TEMPERATURE
T_A
Operating temperature range
T_J
Junction temperature
T_stg
Storage temperature
(1) Performance of ESD testing is according to the ACE-Q100 standard.
DRV3204-Q1
SLVSBT3B – MARCH 2013 – REVISED JULY 2013
MIN
-2
-500
-40
-40
-55
MAX UNIT
2
kV
500
V
125
ºC
150
ºC
175
ºC
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV3204-Q1
PHP
48 PINS
26.1
11.5
7.2
0.2
7.1
0.4
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SUPPLY VOLTAGE AND CURRENT
VB = 12 V, T_A = -40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
SUPPLY INPUT
VB1 ⁽¹⁾
VB supply voltage (motor operation)
VB2 ⁽¹⁾
VB supply voltage (MCU operation)
VB3 ⁽²⁾
VB supply voltage
Ivb
VB operating current
ENABLE = High, no PWM
Ivbq
VB quiescent current
ENABLE = Low
MIN TYP MAX UNITS
5.3
12
18
V
4.5
12
18
V
18
26.5
V
-
18
27
mA
-
50 100
µA
(1) Performance of supply voltage 5.3 V-18 V is according to the ACE-Q100 (Grade 1) standard.
(2) Specified by design.
Copyright © 2013, Texas Instruments Incorporated
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