DRV3204-Q1_15 Datasheet, PDF (24/38 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

DRV3204-Q1
SLVSBT3B – MARCH 2013 – REVISED JULY 2013
Motor Current ^OVADth
OVAD
MTOC SPI Register Flag
tfiltMTOC
tfiltMTOC
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SPI Access
FAULT
read
write 1
to clear
Pre-Driver
Enable
Disable
Enable
(1) MCU must set the FLTCFG.FLGLATCH_EN bit to 1 to get the latch-type operation shown in this figure.
(2) When MTOC condition is detected, FAULT is asserted to low if FE_MTOC bit is 1.
(3) When MTOC condition is detected, Pre Driver is disabled if SE_MTOC is 1.
Figure 17. Motor Overcurrent Event
Regulators
Description:
The regulator block offers 5-V LDO and 3.3-V LDO. The VCC LDO regulates VB down to 5 V with an external
PNP controlled by the regulator block. This 5 V is supplied to MCU and other components.
The VDD regulator regulates VB down to 3.3 V with internal FET and controller. The 5 V LDO is protected
against short to GND fault. Overvoltage and under voltage events of both supplies are detected. The under
voltage of the 5-V LDO is set by SPI.
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