TMS320F28335_08 Datasheet, PDF (43/170 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

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TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008
critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal
latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This
pipelining enables it to execute at high speeds without resorting to expensive high-speed memories.
Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store
conditional operations further improve performance.
The F2823x family is also a member of the TMS320C2000™ digital signal controller (DSC) platform but it
does not include a floating-point unit (FPU).
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSC type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Lowest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the memory bus.)
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSC family of devices, the
F2833x/F2823x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus
bridge multiplexes the various busses that make up the processor Memory Bus into a single bus
consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of
the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2).
Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version
supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).
3.2.4 Real-Time JTAG and Analysis
The F2833x/F2823x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the
devices support real-time mode of operation whereby the contents of memory, peripheral and register
locations can be modified while the processor is running and executing code and servicing interrupts. The
user can also single step through non-time critical code while enabling time-critical interrupts to be
serviced without interference. The device implements the real-time mode in hardware within the CPU. This
is a feature unique to the F2833x/F2823x device, requiring no software monitor. Additionally, special
analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and
generate various user-selectable break events when a match occurs.
3.2.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
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Functional Overview
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