TMS320F28335_08 Datasheet, PDF (139/170 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

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TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008
6.10.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1 Lead:
2 Active:
LR ≥ × t_c(XTIM)
LW ≥ t_c(XTIM)
AR ≥ 2 × t_c(XTIM)
AW ≥ 2 × t_c(XTIM)
3 Lead + Active: LR + AR ≥ 4 × t_c(XTIM)
LW + AW ≥ 4 × t_c(XTIM)
NOTE
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
≥1
XRDACTIVE
≥2
XRDTRAIL
0
XWRLEAD
≥1
XWRACTIVE
≥2
XWRTRAIL
0
X2TIMING
0, 1
or
XRDLEAD
≥2
XRDACTIVE
≥1
XRDTRAIL
0
XWRLEAD
≥2
XWRACTIVE
≥1
XWRTRAIL
0
X2TIMING
0, 1
Examples of valid and invalid timing when using asynchronous XREADY:
Invalid ⁽¹⁾
Invalid ⁽¹⁾
Invalid ⁽¹⁾
XRDLEAD
0
1
1
XRDACTIVE
0
0
1
XRDTRAIL
0
0
0
Valid
1
1
0
Valid
1
2
0
Valid
2
1
0
(1) No hardware to detect illegal XTIMING configurations
XWRLEAD
0
1
1
1
1
2
XWRACTIVE
0
0
1
1
2
1
XWRTRAIL
0
0
0
0
0
0
X2TIMING
0, 1
0, 1
0
1
0, 1
0, 1
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-37.
MODE
1
Example:
2
Example:
3
Example:
4
Example:
Table 6-37. XINTF Clock Configurations
SYSCLKOUT
150 MHz
150 MHz
150 MHz
150 MHz
XTIMCLK
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
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Electrical Specifications 139