TMS320F28335_08 Datasheet, PDF (41/170 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

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TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008
NOTE
• When the code-security passwords are programmed, all addresses between
0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may
be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
Table 3-4 shows how to handle these memory locations.
ADDRESS
0x33FF80 - 0x33FFEF
0x33FFF0 - 0x33FFF5
Table 3-4. Handling Security Code Locations
Code security enabled
Fill with 0x0000
FLASH
Code security disabled
Application code and data
Reserved for data only
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-5.
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Functional Overview
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