TMS320F28335_08 Datasheet, PDF (127/170 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

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TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008
t_d(IDLE-XCOL)
t_p
t_d(WAKE-HALT)
Table 6-19. HALT Mode Switching Characteristics
PARAMETER
Delay time, IDLE instruction executed to XCLKOUT
low
PLL lock-up time
Delay time, PLL lock to program execution resume
• Wake up from flash
– Flash module in sleep state
MIN
32t_c(SCO)
TYP
• Wake up from SARAM
MAX
45t_c(SCO)
131072t_c(OSCCLK)
UNIT
cycles
cycles
1125t_c(SCO) cycles
35t_c(SCO) cycles
Device
Status
GPIOn
(A)
(B)
Flushing Pipeline
X1/X2
or XCLKIN
XCLKOUT
(C)
(E)
(D)
HALT
HALT
PLL Lock-up Time
Wake-up Latency
(G)
(F)
Normal
Execution
t_w(WAKE-GPIO)
t_{d(WAKE−HALT)}
t_p
Oscillator Start-up Time
t_{d(IDLE−XCOL)}
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G. Normal operation resumes.
Figure 6-14. HALT Wake-Up Using GPIOn
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Electrical Specifications 127