TMS320F28335_08 Datasheet, PDF (148/170 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008
www.ti.com
(A) (B)
Lead
WS (Synch)
(C)
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0 XZCS6, XZCS7
XA[0:19]
XRD
XWE0, XWE1 ^(D)
XR/W
XD[0:31], XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_a(A)
t_{su(XRDYsynchL)XCOHL}
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
t_h(XD)XRD
DIN
XREADY(Synch)
t_{h(XRDYsynchL)}
t_{su(XRDHsynchH)XCOHL}
(E)
(F)
t_{e(XRDYsynchH)}
t_{h(XRDYsynchH)XZCSH}
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes
alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0
E. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) t_c(XTIM) – t_{su(XRDYsynchL)XCOH} where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) t_c(XTIM)
Figure 6-27. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
N/A ⁽¹⁾
XRDACTIVE
N/A ⁽¹⁾
XRDTRAIL
N/A ⁽¹⁾
USEREADY
1
X2TIMING
0
XWRLEAD
≥1
(1) N/A = "Don't care" for this example.
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
0 = XREADY
(Synch)
148 Electrical Specifications
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