THS7313 Datasheet, PDF (35/48 Pages) Texas Instruments – 3-Channel Low Power SDTV Video Amplifier with I2C Control, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7313
www.ti.com
SLOS483 – NOVEMBER 2005
Channel Register Bit Descriptions
Each bit of the sub-address (channel selection) control register as described above allows the user to individually
control the functionality of the THS7313. The benefit of this process allows the user to control the functionality of
each channel independent of the other channels. The bit description is decoded in Table 3.
BIT
(MSB)
7, 6
5
4,3
2, 1, 0
(LSB)
Table 3. THS7313 Channel Register Bit Decoder Table
FUNCTION
STC Low Pass Filter Selection
Input MUX Selection
Reserved
Input Bias Mode Selection and
Disable Control
BIT
VALUE(S)
00
01
10
11
0
1
XX
000
001
010
011
100
101
110
111
RESULT
500-kHz Filter – Useful for poor video sync signals
2.5-MHz Filter – Useful for reasonable sync signals
5-MHz Filter – Useful for good sync signals
5-MHz Filter – Useful for good sync signals
Input A Select
Input B Select
Do Not Care
Disable Channel – Conserves Power
Channel On – Mute Function – No Output
Channel On – DC Bias Select
Channel On – DC Bias + 135 mV Offset Select
Channel On – AC Bias Select
Channel On – Sync Tip Clamp with Low Bias
Channel On – Sync Tip Clamp with Mid Bias
Channel On – Sync Tip Clamp with High Bias
Bits 7 (MSB) and 6 – Controls the AC-Sync Tip Clamp Low Pass Filter function. If AC-STC mode is not used,
this function is ignored.
Bit 5 – Controls the input MUX of the THS7313.
Bits 4 and 3 – Reserved for future functionality. The values of these bits do not affect the THS7313.
Bits 2, 1, and 0 (LSB) – Selects the input biasing of the THS7313 and the power-savings function. When
Sync-Tip Clamp is selected, the DC input sink bias current is also selectable.
EXAMPLE – WRITING TO THE THS7313
The proper way to write to the THS7313 is illustrated as follows:
An I²C master initiates a write operation to the THS7313 by generating a start condition (S) followed by the
THS7313 I²C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the THS7313, the master presents the subaddress (channel) it wants to write
consisting of one byte of data, MSB first. The THS7313 acknowledges the byte after completion of the
transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7313
acknowledges the byte. The I²C master then terminates the write operation by generating a stop condition
(P). Note that the THS7313 does not support multi-byte transfers. To write to all three channels – or registers
– this procedure must be repeated for each register one series at a time (i.e., repeat steps 1 through 8 for
each channel).
Step 1
0
I²C Start (Master)
S
Step 2
I²C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I²C-A1 and I²C-A0 pins being tied to either Vs+ or GND.
Step 3
9
I²C Acknowledge (Slave)
A
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