THS7313 Datasheet, PDF (27/48 Pages) Texas Instruments – 3-Channel Low Power SDTV Video Amplifier with I2C Control, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7313
www.ti.com
SLOS483 – NOVEMBER 2005
APPLICATION INFORMATION (continued)
When SAG correction is used, low frequency gain is higher than the high frequency gain (8.1 dB vs. 6 dB). This
gain counter acts the attenuation of the signal due to the increase in the 47-µF capacitor impedance. This
amplifier gain increase is determined by the 33-µF capacitor (and associated internal resistor values) and causes
a Q enhancement to occur at low frequencies – typically at about 15-Hz. The ratio of these capacitors
determines the frequency and amplitude of this enhancement.
The internal resistor values were chosen to optimize the system while using the 47-µF and 33-µF capacitors and
to approximate the performance of a single 330-µF capacitor. These capacitors can be a different value if
desired, but the characteristics of the system are altered accordingly. For example, if 22-µF capacitors is used for
both sections, then there are increases in line tilt and field tilt. But, for some systems this may be considered
acceptable depending on the application. Using larger values, such as 68 µF and 47 µF respectively, decreases
field time distortion even further approaching performance of a single 470-µF capacitor.
It is important to note that the dc gain is about 2.55 V/V. Thus, if the input has a dc bias, the output dc bias is
2.55 times the input. For example, this results in an output bias point of 345 mV for the dc + 135 mV shift.
Additionally, if the ac bias input mode is selected, the dc operating point is Vs/4 X 2.55, or 2.1 V with 3.3-V
supply and 3.2 V with 5-V supply. This additional offset should not hinder the performance of the THS7313 as
there is still plenty of voltage headroom between the dc operating point and the rail-to-rail output capability.
One possible concern about this configuration is the low frequency gain enhancement may cause saturation of
the signal when low power supply voltages - such as 3 V - are used. Thus, the internal resistors were chosen to
minimize the low frequency gain such that saturation is minimized. Other SAG correction parts have much higher
low frequency gain (10 dB or higher), which when coupled with low power supply voltages, can easily create
clipping on the output of the amplifier both dynamically and dc. Other SAG correction parts do not use a resistor
in series with the SAG pin. Neglecting this resistor can result in a large Q enhancement causing possible
saturation issues. These systems typically require much larger feedback capacitor values to minimize this
problem which ultimately minimizes the benefits of SAG correction.
Figure 55 shows a SAG corrected configuration for the THS7313. If a s-video chroma channel is being
configured, there is no reason for SAG correction as the coupling capacitor is typically small at 0.1 µF. Thus,
tying the output pin directly to the SAG output pin is recommended along with a 0.1-µF capacitor.
3.3 V
DAC /
Encoder
CVBS
(THS8200)
R
SDTV
CVBS
Y’
S-Video Y’
S-Video C’
R
480i
576i
G’B’R’
C’
R
CVBS
S-Video Y’
0.1 mF
75 W
0.1 mF
75 W
0.1 mF
DC + 135 mV
1 _NC
NC 20
2 CH.1 IN A CH.1 OUT 19
DC + 135 mV
*
3 _{CH.2 IN A} CH. 1 SAG 18
DC + 135 mV
4 _{CH.3 IN A} CH.2 OUT 17
AC STC
*
5 _{CH.1 IN B} CH. 2 SAG 16
AC STC
6 CH.2 IN B CH.3 OUT 15
AC Bias
7 _{CH.3 IN B} CH. 3 SAG 14
8 I2C-A1
SCL 13
9 I2C-A0
10 _GND
SDA 12
VS+ ¹¹
0.01 mF
47 mF
+
33 mF
+
47 mF
+
33 mF
+
CVBS
75 W ^Out
75 W
S-Video
0.1 mF _{75 W}
+
75 W
Y’
Out
C’
75 W
Out
+Vs
+
100 mF
2
IC
Controller
* (See Note A)
75 W
S-Video C’
External
Input
75 W
A. If the SAG correction capacitors are more than 15 mm from the THS7313, add a 0.01µF capacitor as shown.
Figure 55. Typical SDTV CVBS/Y'/C' System Driving SAG Corrected AC-Coupled Video Lines
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