DS92LX2121 Datasheet, PDF (3/42 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

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DS92LX2121 Pin Diagram
Top View
V_DDIO 31
DIN[8] 32
DIN[9] 33
V_DDD 34
DIN[10] 35
DIN[11] 36
DIN[12] 37
DIN[13] 38
DIN[14] 39
DIN[15] 40
DAP = GND
DS92LX2121
(Top View)
DS92LX2121, DS92LX2122
SNLS330I – MAY 2010 – REVISED APRIL 2013
20 GPO[1]
19 GPO[0]
18 V_DDCML
17 DOUT+
16 DOUT-
15 V_DDT
14 V_DDPLL
13 PDB
12 M/S
11 RES
Figure 3. Serializer - DS92LX2121
40-Pin WQFN (RTA Package)
DS92LX2121 Serializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
5, 4, 3, 2, 1, 40,
39, 38, 37, 36,
35, 33, 32, 30,
29, 28, 27, 26,
25, 24, 23
Inputs, LVCMOS w/
pull down
Parallel data inputs.
PCLK
6
Input, LVCMOS w/ Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0]
22, 21, 20, 19 Output, LVCMOS
SERIAL CONTROL BUS - I²C COMPATIBLE
General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SCL
SDA
M/S
7
Input/Output, Open Clock line for the serial control bus communication
Drain
SCL requires an external pull-up resistor to V_DDIO.
8
Input/Output, Open Data line for the serial control bus communication
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Mode Select
M/S = L, Master mode (default); device generates and drives the SCL clock
12
Input, LVCMOS w/
pull down
line. Device is connected to a slave peripheral on the bus. (Serializer initially
starts up in Standby mode and is enabled through remote wakeup by the
Deserializer)
M/S = H, Slave; device accepts SCL clock input
CAD
9
Input, analog
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
Copyright © 2010–2013, Texas Instruments Incorporated
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