DS92LX2121 Datasheet, PDF (26/42 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX2121, DS92LX2122
SNLS330I – MAY 2010 – REVISED APRIL 2013
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SYNCHRONIZING MULTIPLE LINKS
For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose
Input/ Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To
synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form
of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bi-directional control channel, there will be a time variation of the GPI/GPO signals arriving at the different
target devices (between the parallel links). The maximum latency delta (t1) of the GPI/GPO data transmitted
across multiple links is 25 μs.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
The maximum time (t1) between the rising edge of GPI/GPO (i.e. sync signal) arriving at Camera A and Camera
B is 25 μs.
DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t1
Figure 29. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
The DS92LX2121 / DS92LX2122 has up to 4 GPO and 4 GPI on the Serializer and Deserializer respectively.
The GPI/GPO maximum switching rate is up to 66 kHz for communication between Deserializer GPI to Serializer
GPO.
AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and
the back-channel link. Control pins allow the system to initiate the test and set the duration. A HIGH on PASS pin
indicates that all payloads received during the test were error free during the BIST duration test. A LOW on this
pin at the conclusion of this test indicates that one or more payloads were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST starts when BISTEN goes HIGH. BIST ends when
BISTEN goes LOW. PASS flag will go HIGH when no errors detected after BIST Duration completes. Any errors
detected after the BIST Duration are not included in PASS logic.
The following diagram shows how to perform system AT SPEED BIST:
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