THS6022 Datasheet, PDF (28/38 Pages) Texas Instruments – 250-mA DUAL DIFFERENTIAL LINE DRIVER

THS6022
250-mA DUAL DIFFERENTIAL LINE DRIVER
SLOS225C – SEPTEMBER 1998 – REVISED JANUARY 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6022 has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 55. A minimum value of 15 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kΩ
Input
1 kΩ
_
THS6022
+
15 Ω
Output
CLOAD
Figure 55. Driving a Capacitive Load
PCB design considerations
Proper PCB design techniques in two areas are important to assure proper operation of the THS6022. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6022 is a
high-speed part, the following guidelines are recommended.
D Ground plane – It is essential that a ground plane be used on the board to provide all components with a
low inductive ground connection. Although a ground connection directly to a terminal of the THS6022 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and
it provides the path for heat removal.
D Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This
is especially true in the noninverting configuration. An example of this can be seen in Figure 56, which shows
what happens when a 1.0 pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of
the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While
the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is
because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in
the noninverting configuration. This can be seen in Figure 57, where a 27-pF capacitor adds only 0.5 dB
of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor
decreases. While this can initally appear to be a faster and better system, overshoot and ringing are more
likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input
node should always be performed for stable operation.
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