DRV8432_15 Datasheet, PDF (26/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
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System Design Recommendations (continued)
9.4.4 Mode Select Pin
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
9.4.5 Parallel Mode Operation
For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required
after the output pins (for example, OUT_A and OUT_B) before connecting the two channels together. This will
help to prevent any shoot through between two paralleled channels during switching transient due to mismatch of
paralleled channels (for example, processor variation, unsymmetrical PCB layout, etc).
9.4.6 TEC Driver Application
For TEC driver or other non-motor related applications (for example, resistive load or dc output), a low-pass LC
filter can be used to meet the requirement.
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