TLC320AD81C Datasheet, PDF (25/47 Pages) Texas Instruments – Stereo Audio Digital Equalizer DC

3.5 Audio Serial Port Timing Requirements (see Note 3)
PARAMETER
MIN TYP
f(SCLK)
Frequency, SCLK
32 fs†
tr(SCLK) Rise time, SCLK (see Note 4)
5 16.3
tf(SCLK) Fall time, SCLK (see Note 4)
5 16.3
td(SLR)
Delay time, SCLK rising to LRCLK edge (see Note 5)
50
td(SDOUT) Delay time, SDOUT valid from SCLK falling
tsu(SDIN) Setup time, SDIN before SCLK rising edge
10
th(SDIN) Hold time, SDIN from SCLK rising edge
100
† _{Valid in 16-bit left justified mode only.}
NOTES: 3. Timing relative to 256 fs MCLK.
4. SCLK rising and falling are measured from 20% to 80%.
5. The rising edge of SCLK must not occur at the same time as either edge of LRCLK.
MAX
64 fs
25
25
100
UNIT
MHz
ns
ns
ns
ns
ns
ns
3.6 I²C Serial Port Timing Requirements
PARAMETER
MIN MAX UNIT
f(scl)
SCL clock frequency
0 100 kHz
tBUF
Bus free time between start and stop
4.7
µs
tw(low)
Pulse duration, SCL clock low (see Note 6)
4.7
µs
tw(high)
Pulse duration, SCL clock high (see Note 7)
4
µs
th(STA)
Hold time, repeated start
4
µs
tsu(STA)
th(DAT)
Setup time, repeated start
Hold time, data
4.7
20 µs
0†
µs
tsu(DAT) Setup time, data
250
ns
tr
Rise time for SDA and SCL
1000 ns
tf
Fall time for SDA and SCL
300 ns
tsu(STO) Setup time for stop condition
4
µs
† _{A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the}
falling edge of SCL.
NOTES: 6. tw(low) is measured from the end of tf to the beginning of tr.
7. tw(high) is measured from the end of tr to the beginning of tf.
3–3