TLC320AD81C Datasheet, PDF (14/47 Pages) Texas Instruments – Stereo Audio Digital Equalizer DC

2.5 Serial Audio Interface
2.5.1 I²S Serial Format
SCLK
LRCLK = fs
SDIN
X MSB
LSB
X MSB
LSB
SDOUT
X MSB
LSB
X MSB
LSB
Left Channel
Right Channel
Figure 2–1. I²S Compatible Serial Format
2.5.2 Protocol
1. LRCLK = Sampling frequency (f_s)
2. Left channel is transmitted when LR is low
3. SCLK = 64 × LRCLK. SCLK is sometimes referred to as the bit clock.
4. Serial data is sampled with the rising edge of SCLK.
5. Serial data is transmitted on the falling edge of SCLK.
6. LRCLK must have a 50% duty cycle
2.5.3 Implementation
1. LRCLK and SCLK are both inputs
2.5.4 Timing
See Figure 4–1 for I²S timing.
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