TLC320AD81C Datasheet, PDF (12/47 Pages) Texas Instruments – Stereo Audio Digital Equalizer DC

1.5 Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AVDD_DAC
AVDD_PLL
AVSS_DAC
AVSS_PLL
CAP_VREF
CS1
CS2
21
I Analog power supply for the DAC
6
I Analog power supply for the PLL
18
I Analog ground for the DAC
5
I Analog ground for the PLL
14
O 10 µF // 0.1 µF to AVSS_DAC (recommended values)†
31
I I2C address bit A0; low = 0, high = 1
32
I I2C address bit A1; low = 0, high = 1
DM
29
I
De-emphasis at 44.1 kHz; off when pin low, on when pin high (default = on
when pin not driven or biased)
DVDD
34
I Digital power supply
DVDD_DAC
20
I Digital power supply for the DAC
DVSS
33
I Digital ground
DVSS_DAC
19
I Digital ground for the DAC
LRCLK
3
I Serial audio left/right clock sampling frequency (fs)
MCLK
2
I Master clock
NC
11–13 15, 17,
23, 24 26–28
No connection
OUT_L
22
O Analog output voltage left channel
OUT_R
16
O Analog output voltage right channel
PLL–FLT
7
O C1 = 1500 pF // R1 = 27.4 Ω + C2 = 0.068 µF (recommended values)
RESERVED
8, 9, 30
For internal use only, must be connected to GND
RESET
SCL
10
I Reset, low = current state, high = reinitialized the device
36
I/O Slave serial I2C clock
SCLK
SDA
4
I Shift clock (bit clock)
35
I/O Slave serial I2C data
SDIN1
37
I Serial audio data input one
SDIN2
38
I Serial audio data input two
SDOUT
1
O Serial audio data output
SMUTE
25
I
Soft mute off when pin low; on when pin high (default = off when pin not
driven or biased)
† _{If only one capacitor is used, a 10-µF capacitor connected to AVSS_DAC should be used.}
1–4