AM1810_15 Datasheet, PDF (245/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

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AM1810
SPRS709D – NOVEMBER 2010 – REVISED MARCH 2014
6.33 Programmable Real-Time Unit Subsystem (PRUSS) With PROFIBUS
The Programmable Real-Time Unit Subsystem with PROFIBUS implements the PROFIBUS (PROFIBUS-
DP) fieldbus communication protocol. It works in conjunction with the UART1 or UART2, one of which is
designated as the PROFIBUS interface. The tasks such as real-time frame handling, message
transmission, frame validation and communication with ARM CPU are performed by the two
Programmable Real-time Units (PRU).
The PROFIBUS stack (Layer 7, DP-Protocol) and the industrial application are run on the ARM processor.
The PRUSS with PROFIBUS communicates to the ARM host CPU through interrupts. All process data
handling like cyclic, acyclic, and service access point (SAP) between the PROFIBUS stack on ARM and
the PRU is through the internal memory. The PRUSS with PROFIBUS supports up to 12 Mbaud data rate
with 11 bit minimum response time.
The AM1810 based PROFIBUS slave solution has been certified for PROFIBUS compliance by the
certification labs of PROFIBUS and PROFINET International.
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
• Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
• An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 6-137 and in Table 6-138. Note that these two memory maps are implemented
inside the PRUSS and are local to the components of the PRUSS.
Table 6-137. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
0x0000 0000 - 0x0000 0FFF
PRU0
PRU0 Instruction RAM
PRU1
PRU1 Instruction RAM
Table 6-138. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
0x0000 0000 - 0x0000 01FF
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
0x0000 2200 - 0x0000 3FFF
0x0000 4000 - 0x0000 6FFF
0x0000 7000 - 0x0000 73FF
0x0000 7400 - 0x0000 77FF
0x0000 7800 - 0x0000 7BFF
PRU0
Data RAM 0 ⁽¹⁾
Reserved
Data RAM 1 ⁽¹⁾
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
PRU1
Data RAM 1 ⁽¹⁾
Reserved
Data RAM 0 ⁽¹⁾
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
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