AM1810_15 Datasheet, PDF (137/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

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AM1810
SPRS709D – NOVEMBER 2010 – REVISED MARCH 2014
Table 6-51. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
0x01D0 1018
0x01D0 101C
ACRONYM
AFIFOREV
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
REGISTER DESCRIPTION
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
Read FIFO control register
Read FIFO status register
6.15.2 McASP Electrical Data/Timing
6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-52 and Table 6-54 assume testing over recommended operating conditions (see Figure 6-30 and
Figure 6-31).
Table 6-52. Timing Requirements for McASP0 (1.2V, 1.1V)⁽¹⁾⁽²⁾
NO.
1 t_c(AHCLKRX)
Cycle time, AHCLKR/X
2 t_w(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3 t_c(ACLKRX)
Cycle time, ACLKR/X
AHCLKR/X ext
4 t_w(ACLKRX)
Pulse duration, ACLKR/W high or low AHCLKR/X ext
5
t_{su(AFSRX-ACLKRX)}
Setup time,
AFSR/X input to ACLKR/X⁽⁴⁾
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
6 t_{h(ACLKRX-AFSRX)}
Hold time,
AFSR/X input after ACLKR/X⁽⁴⁾
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
7 t_{su(AXR-ACLKRX)}
Setup time,
AXR0[n] input to ACLKR/X⁽⁴⁾⁽⁵⁾
AHCLKR/X int
AHCLKR/X ext
8 t_{h(ACLKRX-AXR)}
Hold time,
AXR0[n] input after ACLKR/X⁽⁴⁾⁽⁵⁾
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
1.2V
MIN
MAX
25
12.5
25 ⁽³⁾
12.5
11.5
4
4
-1
1
1
11.5
4
-1
3
3
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) This timing is limited by the timing shown or 2P, whichever is greater.
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
1.1V
MIN
MAX
28
14
28 ⁽³⁾
14
12
5
5
-2
1
1
12
5
-2
4
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 137
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