AM1810_15 Datasheet, PDF (220/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

AM1810
SPRS709D – NOVEMBER 2010 – REVISED MARCH 2014
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6.26.2 uPP Electrical Data/Timing
Table 6-116. Timing Requirements for uPP (see Figure 6-69, Figure 6-70, Figure 6-71, Figure 6-72)
1.2V
1.1V
1.0V
NO.
UNIT
MIN MAX MIN MAX MIN MAX
1 t_c(INCLK)
Cycle time, CHn_CLK
SDR mode 13.33
20
26.66
ns
DDR mode 26.66
40
53.33
2 t_w(INCLKH)
Pulse width, CHn_CLK high
SDR mode
5
8
10
ns
DDR mode
10
16
20
3 t_w(INCLKL)
Pulse width, CHn_CLK low
SDR mode
5
8
10
ns
DDR mode
10
16
20
4 t_{su(STV-INCLKH)} Setup time, CHn_START valid before CHn_CLK high
4
5.5
6.5
ns
5
t_{h(INCLKH-STV)}
Hold time, CHn_START valid after CHn_CLK high
0.8
0.8
0.8
ns
6 t_{su(ENV-INCLKH)} Setup time, CHn_ENABLE valid before CHn_CLK high
4
5.5
6.5
ns
7 t_{h(INCLKH-ENV)} Hold time, CHn_ENABLE valid after CHn_CLK high
0.8
0.8
0.8
ns
8
t_{su(DV-INCLKH)}
Setup time, CHn_DATA/XDATA valid before CHn_CLK
high
4
5.5
6.5
ns
9
t_h(INCLKH-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high 0.8
0.8
0.8
ns
10 t_{su(DV-INCLKL)}
Setup time, CHn_DATA/XDATA valid before CHn_CLK
low
4
5.5
6.5
ns
11 t_h(INCLKL-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
0.8
0.8
0.8
ns
19 t_{su(WTV-INCLKL)} Setup time, CHn_WAIT valid before CHn_CLK high
10
12
14
ns
20 t_{h(INCLKL-WTV)}
21 t_c(2xTXCLK)
Hold time, CHn_WAIT valid after CHn_CLK high
Cycle time, 2xTXCLK input clock⁽¹⁾
0.8
0.8
0.8
ns
6.66
10
13.33
ns
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-117. Switching Characteristics Over Recommended Operating Conditions for uPP
1.2V
NO.
PARAMETER
MIN MAX
12 t_c(OUTCLK)
Cycle time, CHn_CLK
SDR mode
DDR mode
13.33
26.66
13 t_w(OUTCLKH)
Pulse width, CHn_CLK high
SDR mode
5
DDR mode
10
14 t_w(OUTCLKL)
Pulse width, CHn_CLK low
SDR mode
5
DDR mode
10
15 t_{d(OUTCLKH-STV)} Delay time, CHn_START valid after CHn_CLK high
2
11
16 t_{d(OUTCLKH-ENV)} Delay time, CHn_ENABLE valid after CHn_CLK high
2
11
17 t_{d(OUTCLKH-DV)} Delay time, CHn_DATA/XDATA valid after CHn_CLK high 2
11
18 t_{d(OUTCLKL-DV)} Delay time, CHn_DATA/XDATA valid after CHn_CLK low
2
11
1.1V
MIN MAX
20
40
8
16
8
16
2
15
2
15
2
15
2
15
1.0V
MIN MAX
26.66
53.33
10
20
10
20
2
21
2
21
2
21
2
21
UNIT
ns
ns
ns
ns
ns
ns
ns
220 Peripheral Information and Electrical Specifications
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